Host
Intel Core Ultra 9 285K · 24 cores
Platform
linux/amd64
Go
go1.26.0
CPython
python:3.13-slim
PyPy
pypy:3.10-slim
Runs / combo
10 + 2 warmup

LRU cache

Hand-rolled LRU (doubly-linked list + map) servicing 100k mixed get/put operations.

Compile time · median (cold)

median of 10 runs

Native Gocompiled
180 ms109×
Piko interpbytecode VM
1.66 msbaseline
CPython 3.13bytecode VM
449 µs0.27×
PyPy 7.3tracing JIT
368 µs0.22×
Ttengobytecode VM
313 µs0.19×
Sscriggobytecode VM
n/a
Mmvmbytecode VM
461 µs0.28×
YyaegiAST walker
567 µs0.34×

Full statistics

RunnerNCompileRuntimeP95StddevRSSvs pikoStatus
Native Gocompiled10180 ms16.2 ms16.7 ms527 µs69 MiB109×OK
Piko interpbytecode VM101.66 ms155 ms155 ms351 µs183 MiB1.00×OK
CPython 3.13bytecode VM10449 µs98.7 ms101 ms1.92 msn/a0.27×OK
PyPy 7.3tracing JIT10368 µs15.0 ms16.3 ms516 µsn/a0.22×OK
tengobytecode VM10313 µs174 ms177 ms5.21 ms872 MiB0.19×OK
scriggobytecode VM0n/an/an/an/an/an/aunsupported
mvmbytecode VM10461 µs323 ms361 ms20.8 ms63 MiB0.28×OK
yaegiAST walker10567 µs966 ms996 ms23.9 ms66 MiB0.34×OK
Workload & symmetry rules

Workload

A cache of size 4096 sees a 100,000-op trace of 70% reads / 30% writes. Implement using a hash map plus a doubly-linked list for recency. Print the final hit/miss totals.

Symmetry rules

  • Hand-rolled linked list; no OrderedDict, no functools.lru_cache.
  • Generic map / dict for indexing.
Source code