Host
Intel Core Ultra 9 285K · 24 cores
Platform
linux/amd64
Go
go1.27.0
CPython
python:3.14-slim
PyPy
pypy:3.11-slim
Runs / combo
7 + 2 warmup

LRU cache

Hand-rolled LRU (doubly-linked list + map) servicing 100k mixed get/put operations.

Compile time · median (cold)

median of 7 runs

Native Gocompiled
109 ms57.7×
Pipitbytecode VM
1.89 msbaseline
CPython 3.14bytecode VM
570 µs0.30×
PyPy 7.3tracing JIT
406 µs0.21×
Ttengobytecode VM
342 µs0.18×
Sscriggobytecode VM
n/a
Mmvmbytecode VM
483 µs0.26×
YyaegiAST walker
467 µs0.25×

Full statistics

RunnerNCompileRuntimeP95StddevRSSvs pipitStatus
Native Gocompiled7109 ms15.4 ms15.9 ms304 µs1.62 GiB57.7×OK
Pipitbytecode VM71.89 ms87.4 ms106 ms6.77 ms591 MiB1.00×OK
CPython 3.14bytecode VM7570 µs84.7 ms85.5 ms399 µsn/a0.30×OK
PyPy 7.3tracing JIT7406 µs17.2 ms18.8 ms905 µsn/a0.21×OK
tengobytecode VM7342 µs171 ms188 ms12.6 ms1.68 GiB0.18×OK
scriggobytecode VM0n/an/an/an/an/an/aunsupported
mvmbytecode VM7483 µs281 ms286 ms3.09 ms1.68 GiB0.26×OK
yaegiAST walker7467 µs754 ms778 ms16.7 ms1.68 GiB0.25×OK
Workload & symmetry rules

Workload

A cache of size 4096 sees a 100,000-op trace of 70% reads / 30% writes. Implement using a hash map plus a doubly-linked list for recency. Print the final hit/miss totals.

Symmetry rules

  • Hand-rolled linked list; no OrderedDict, no functools.lru_cache.
  • Generic map / dict for indexing.
Source code